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Automatic RF MESFET Amplifier
Drain-Current Controllers
Table 22. SCLR (Write)
BIT NAME
X
DATA BIT
D15–D7
RESET STATE
X
Don’t care.
FUNCTION
Write the following sequence to perform a full reset and return all internal
registers to their respective reset state:
FULLRESET
D6
N/A
Write to the software clear register once with FULLRESET = 0 and
ARMRESET = 1. Write a second word to the software clear register with
FULLRESET = 1 and ARMRESET = 0.
The full reset takes effect after completion of the second write to this
register.
After a full software reset, the internal registers return to their power-on
state, but the internal oscillator remains running (unlike at power-up).
ARMRESET
D5
0
After a full software reset, it is not necessary to set the FULLPD bit to 0
(as it is on a normal power-on reset) before attempting any other
commands. The BUSY output is set high and the ALU initializes internal
RAM before setting BUSY low.
ALMSCLR
D4
N/A
Set to 1 to reset all ALARM threshold registers and the ALARM flag
register.
Set to 1 to force the ALU to clear the pointers and lookup value cache to
CACHECLR
D3
N/A
their power-up values. This forces an LUT operation and a V DAC(CODE)
calculation for the next sample, regardless of whether the sample
produces a table pointer that is different.
FIFOCLR
DAC2CLR
DAC1CLR
D2
D1
D0
N/A
N/A
N/A
Set to 1 to reset the FIFO address pointers and clear the FIFO’s contents.
Set to 1 to reset the channel 2 DAC input and output registers.
Set to 1 to reset the channel 1 DAC input and output registers.
Table 23. LUTADD (Write)
BIT NAME
LUTWORD7–
LUTWORD0
LUTADD7–
LUTADD0
DATA BIT
D15–D8
D7–D0
RESET STATE
0000 0000
0000 0000
FUNCTION
Set these 8 bits to determine the number of LUT words to be
read/written.
Set these 8 bits to determine the base address for the read/write
operation.
SCLR (Write)
write to this register.
Write to the software clear register to reset all of the
internal registers, clear the internal ALU or reset the FIFO
pointers and clear the FIFO. This register also resets the
ALARM threshold registers, ALARM flag register and the
?
It is recommended a FULLRESET be completed after
power-up. See Appendix: Startup Code Example for
sample startup code.
DAC registers. Set the command byte to 74h to write to
the software clear register. See Table 22. Bits D15–D7
are don’t care. The FULLRESET bit, D6, and ARMRESET
bit, D5, provide functionality for a full reset. Write the
following sequence to perform a full reset and return all
internal register bits to their respective reset state:
? Write to the software clear register once with
FULLRESET = 0 and ARMRESET = 1.
? Write a second word to the software clear register
with FULLRESET = 1 and ARMRESET = 0. The full
reset takes effect after completion of the second
Set the ALMSCLR bit, D4, to 1 to reset all ALARM thresh-
old register bits and the ALARM flag register bits. Set the
CACHECLR bit, D3, to 1 to force the ALU to clear the
pointers and lookup value cache to their power-up val-
ues. This forces a LUT operation and a V DAC(CODE) cal-
culation for the next sample, regardless of whether the
sample produces a table pointer that is different. Set the
FIFOCLR bit, D2, to 1, reset the FIFO address pointers,
and clear the FIFO’s contents. Set the DAC2CLR bit, D1,
to 1 to reset the channel 2 DAC input and output register
bits. Set the DAC1CLR bit, D0, to 1 to reset the channel 1
DAC input and output register bits.
48
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